Mentor: Verification & Validation
M.Tech (EE), IIT-Madras-B.Tech (DCE)-Gold Medallist
Digital Design/Verification Expert, Digital Protocol Design and SV/UVM Verification Team Mentor, he brings 18+ years of industry experience in various fields like RTL Design, RTL Verification, FPGA Prototyping, Pre-Silicon Verification, Emulation, Post-silicon Validation and System Testing at large Semiconductor companies, during working on state of the art products.
Prior to Logic Fruit, Sandeep worked in companies like INTEL, Ittiam Systems, Texas Instruments, Ciena and C-DOT. Sandeep has a very good understanding of protocols namely AHB, DigRF, CSI, DSI, Dphy, Mphy, Gige, Interlaken, SPI4.2 PCIe, HDCP, DP etc.