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The TCC is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on. TCC Codes are part of recently invented ‘Iterative decoders’, which involves multiple iterations to improve the performance. Iterative decoder shows improved performance compared to legacy convolution codes.
TCC codes outperform Convolution codes by 3-4 dB and are characterized by a ‘water-fall’ region in their SNR – BER curve. There is a SNR threshold after which BER decreases very rapidly. Hence, TCC codes have found their place in most of the latest wireless applications.

  • Fully synchronous design using a single clock
  • Code Rate support of1/3, 1/2, 2/3, 3/4, 4/5, 5/6, 6/7 and 8/9
  • Block length support from 48 bit to 4800 bits
  • Block length and Code-Rate can be changed block by block at run time
  • Number of Iterations 8 or User-defined/Automatic
  • Configurable soft input bit width
  • Provides clock enable support at input and output
  • Easy-to-use interface with handshaking signals
  • Supports all FPGA devices
  • Maximum synthesizable frequency is 100MHz to 200 MHZ depending on target FPGA
  • More than 10 Mbps throughput @ 200MHz clk
  • Use of Duo-Binary TCC to achieve good performance with Puncturing enabled
  • Decoding algorithm : Max-Log MAP
  • Sliding Windowing approach at decoder to reduce memory requirement
  • Modulo Arithmetic is used to achieve high throughput

IP Data Fact Sheet

ConfigurationResources Utilization

Throughput

@ 200 MHz

Max Block SizeLUTsFFsBlock RAMs(Mbps)
4.8K15K15K2010
Provided with IP
DocumentsProduct Specification
Design FilesRTL-VHDL (Optional)
Reference DesignProvided
System Generator ModelProvided (Optional)
Matlab Bit-Accurate ModelProvided (Optional)

Design Tools

SimulationModelSim SE
Synthesis ToolXilinx ISE /Altera Quartus
Support
Three Month Support Provided

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