PCIe has experienced multiple emendations since its inception; currently new motherboards started supporting version 4.0 and the version 5.0 supported motherboards are expected to hit the market by 2022.
PCIe 4.0 and 5.0 was formally released in 2017 and 2019 respectively. Throughout the entire existence of PCI advancement, this might be the first run through another standard has been done before the previous had even dispatched in the consumer market.
Logic Fruit Technologies has designed & implemented ARINC 818 Transmitter & Receiver IP Core supporting multiple line rates up to 4.25Gbps. The IP core has been developed by taking DO-254 Methodology and is having CEMILAC certification.
The critical feature of any new PCIe version is that it doubles the bandwidth from the previous generation. PCIe 4.0 and 5.0 doesn’t differ from this behaviour and continues the trend alongwith maintaining the backwards compatibility.
Following are the key pickups :
Physical Layer Changes-
- Back-to-back EIEOS signals added and Start of Data Stream Ordered Set (SDS) updated.
- Modified Training Sequences (TS1 & TS2) with new fields for alternate protocol ID and enhanced precoding support.
Similarities:
- Fundamental PCIe elements such as the encoding method and target bit error rate (BER) stayed consistent.
- Signaling and scrambling schemes additionally remained reliable with PCIe Gen 4.0.
PCIe 5 .0 advantage :
- High-bandwidth applications such as AI and ML can take full advantage of higher transfer rates of PCIe 5.0.
- Due to higher speed interconnections between system devices PCIe 5.0 will be a game changer for Data center / cloud computing.
- Improved signal integrity and mechanical performance of connectors.
Conclusion :
PCIe 5.0 represents a doubling over PCIe 4.0 with a raw speed of 32GT/s vs. 16GT/s translating to aggregate bandwidth for a x16 link of ~128GB/s vs. ~64GB/s.
