CORDIC
- Supports Vector Rotation, and Angle Calculation.
- Extended CORDIC angle range from first quadrant to the full circle.
- Provision for amplitude compensation scaling module.
- Output rounding modes of rounding/flooring/truncation.
- Both Pipelined and Non-Pipelined architectures are available.
- Programmable internal add-sub precision.
- Programmable internal add-sub iterations.
- Input/output format – 2’s complement.
- Easy-to-use interface with handshaking signals.
- Supports all FPGA devices.
- Maximum synthesizable frequency is 200MHz.
IP Data Fact Sheet | ||||||
Configuration | Resources Utilization | Throughput @ 200 MHz | ||||
Input bit-12 Iteration-12 | LUTs | FFs | Block RAMs | (Mbps) | ||
Pipelined | 1300 | 1200 | 0 | 200 | ||
Non-Pipelined | 400 | 200 | 0 | 12 | ||
Provided with IP | ||||||
Documents | Product Specification | |||||
Net-list | EDIF/NGC/NGO/QXP | |||||
Design Files | RTL-VHDL (Optional) | |||||
Reference Design | Provided | |||||
System Generator Model | Provided (Optional) | |||||
Matlab Bit-Accurate Model | Provided (Optional) | |||||
Design Tools | ||||||
Simulation | ModelSim SE | |||||
Synthesis Tool | Xilinx ISE 14.4/Altera Quartus 10.1 | |||||
Support | ||||||
Three Month Support Provided |