The BCH decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on.
- Fully synchronous design using a single clock
- Code block length variable from 7 to 255 symbols with up to 200 check symbols
- Block length can be changed at compile time
- No of check symbols can be varied block by block in run time
- Error correcting capability (t) can be changed at runtime with condition t ≤ n/8
- Automatically configured by user-entered parameters
- Provides clock enable support at input and output
- Easy-to-use interface with handshaking signals
- Supports all FPGA devices
- Maximum synthesizable frequency is 250MHz
- Configurable soft input bit width
- Run time configurable error correcting capability
- Generates decoding failure in case of uncorrectable errors
IP Data Fact Sheet | ||||||
| Configuration | Resources Utilization | Throughput At P = 4 @ 60 MHz | ||||
| t | channels | n | LUTs | FFs | (Mbps) | |
| 31 | 2 | 255 | 12231 | 12213 | 2 | |
| 15 | 2 | 255 | 6546 | 6822 | 2.8 | |
| 15 | 4 | 255 | 11993 | 12649 | 4.8 | |
| 15 | 2 | 127 | 6096 | 5526 | 2 | |
| 7 | 4 | 63 | 4753 | 4638 | 3.5 | |
| 7 | 2 | 63 | 2324 | 2514 | 2 | |
| Provided with IP | ||||||
| Documents | Product Specification | |||||
| Design Files | RTL | |||||
| Test Bench | Provided | |||||
| Octave Model | Provided | |||||
| Simulation Model | VHDL | |||||
Design Tools | ||||||
| Simulation | ModelSim SE 6.4c | |||||
| Synthesis Tool | Xilinx ISE 14.2 | |||||
| Support | ||||||
| Provided by Logic Fruit Technologies | ||||||
