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AWGN Channel Simulator IP

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AWGN Channel Simulator IP

  • Based on Box Muller Algorithm
  • Tail Accuracy of 6.6σ
  • Effective Period Length of 2255
  • Flat Noise Spectrum
  • Supports all FPGA devices
  • Maximum synthesizable frequency is 200MHZ depending on target FPGA
  • Configurable input Seed value to generate different AWGN stream
  • Bit Accurate MATLAB model available.
  • SNR input ranges from – 30 to 50 dB

IP Data Fact Sheet

Resources Utilization

LUTsFFsBlock RAMMultipliers
60540522

Provided with IP

DocumentsProduct Specification
Design FilesRTL-VHDL (Optional)
Reference DesignProvided
System Generator ModelProvided (Optional)
Matlab Bit-Accurate ModelProvided (Optional)

Design Tools

SimulationModelSim SE
Synthesis ToolXilinx ISE /Altera Quartus
Support
Three Month Support Provided

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