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Author page: Amar Tyagi

SPI Master/Slave Controller

SPI Master/Slave Controller Support for both SPI Master and Slave. Multi Master Support. 8 Slave Select Lines. In Master Mode – bit rate generated is System Clock/2. In Slave Mode – bit rate supported is ≤ System Clock/8. Programmable SCK Phase and Polarity. Supports Repeated Start and Fast Read Operation. Transaction Layer implemented in HDL Source code as well. Programmable…

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High Speed Transceivers (GTX, GXB)

High Speed Transceivers (GTX, GXB) running upto 12 Gbps High speed transceivers (GTX) is one of the key expertise when working with high-speed FPGA design. Some of the example where it may be required is given below For different high speed interfaces e.g. PCIe (8 Gbps), Giga-bit Ethernet, SRIO, USB 3.0. To connect between FPGA and DSP using SRIO. In…

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LVDS running upto 1 Gbps line rate

LVDS running up to 1 Gbps line rate LVDS interface is one of the key expertise when working with high-speed FPGA design. Some of the example where it may be required is given below To provide a high speed data interfaces between two FPGAs on the board (up-to 1000 MHz) To interface with high speed DAC-ADC (up-to 1 GHz) For…

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AXI-Full and AXI-Lite Interfaces

AXI-Full and AXI-Lite Interfaces AXI Lite Interface AXI Lite Interface has Master components, Interconnect, and Slave Components . User Logic connected to AXI-Lite Masters and AXI-Lite Slaves, and AXI-Lite Master and Slaves are connected via AXI-Lite Interconnect. All the blocks AXI-lite Master and AXI-lite Slave and AXI-Lite Interconnect blocks shown in below figure are implemented in Generic VHDL, so that…

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DDR2/3 Interface Engine

DDR2/3 Interface Engine Most of high speed FPGA based project requires multiple master accessing a single DDR3 module. Some example project (which we’ve executed can be) Different Video Processing Algorithm IPs accessing DDR3 at the same time. IQ Data Streaming from Host PC to DDR memory on Card through PCIe/Ethernet interface and also streaming from DDR to multiple high-speed DAC…

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FFT

FFT Transform Size n = 2m, m = 5 to 16. Supports both FFT/IFFT operations at run-time. Highly optimized Radix 23 architecture. Output rounding modes of rounding/flooring/truncation. Both Pipelined and Non-Pipelined architectures are available. Internal bit-width are chosen so as to minimize quantization noise. Programmable internal data-path width of various stages. Decimation in Frequency (DIF) FFT algorithm. Input/Output in natural…

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CORDIC

CORDIC Supports Vector Rotation, and Angle Calculation. Extended CORDIC angle range from first quadrant to the full circle. Provision for amplitude compensation scaling module. Output rounding modes of rounding/flooring/truncation. Both Pipelined and Non-Pipelined architectures are available. Programmable internal add-sub precision. Programmable internal add-sub iterations. Input/output format – 2’s complement. Easy-to-use interface with handshaking signals. Supports all FPGA devices. Maximum synthesizable…

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LDPC Codec for CVS Applications

Low Density Parity Check Codec for CVS Applications Fully synchronous design using a single clock Code Rate support of ½ and Block length support of 2K bits (coded) Configurable soft input bit width Very small decoding latency of the order of 10’s of us Impressive BER performance (Eb/No = 2~2.5 dB @ 10-6 BER) Decoding algorithm : Offset Min-Sum Support…

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Fading Channel Simulator IP

Fading Channel Simulator IP Fading Channel Model Supported : Rican, Rayleigh, Watterson channel( for HF ) Up to 16 taps supported Doppler Spectrum Supported: Jakes, Gaussian and Bi-Gaussian Each tap can be configured individually (type of channel) Max Doppler Ratio = 105, Min Doppler Ratio = 102 Maximum synthesizable frequency is 200MHZ depending on target FPGA Configurable input Seed value…

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AWGN Channel Simulator IP

AWGN Channel Simulator IP Based on Box Muller Algorithm Tail Accuracy of 6.6σ Effective Period Length of 2255 Flat Noise Spectrum Supports all FPGA devices Maximum synthesizable frequency is 200MHZ depending on target FPGA Configurable input Seed value to generate different AWGN stream Bit Accurate MATLAB model available. SNR input ranges from – 30 to 50 dB IP Data Fact…

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