AXI-Full and AXI-Lite Interfaces

On-chip communication: Perhaps the most important protocol under the Advanced Microcontroller Bus Architecture is the Advanced eXtensible Interface. 

Introduced in 2003 with the AMBA3 specification, AXI was radically rejuvenated with the introduction of AMBA4 in 2010 by the introduction of three different protocols, that is, AXI4, AXI4-Lite, and AXI4-Stream, which facilitate operations ranging from high-performance memory-mapped operations down to simple control and status communications. 

It is therefore important to get the feel of the real essence and nuances of AXI-Full and AXI-Lite interfaces, since therein lies the way to use these interfaces towards a modern FPGA, good design, and integrated systems that are diverse and flexible, providing efficiency across various applications.

In this blog, we will delve into AXI full and AXI lite interfaces

Understanding AXI Interfaces

A communication bus protocol for on-chip use, Advanced eXtensible Interface (AXI) is a component of the Advanced Microcontroller Bus Architecture specification (AMBA). 

AXI was first made available in 2003 along with the AMBA3 specification. 

2010 saw the release of AMBA4, which included new protocol definitions for AXI4, AXI4-Lite, and AXI4-Stream. ARM provides AXI’s specifications without charge, and it is royalty-free.

Due to the multiple optional signals that AMBA AXI offers, AXI is a flexible bus suitable for a wide range of applications. These signals can be incorporated based on the particular requirements of the design.

The specification has explicit signals and descriptions to incorporate N: M interconnects, which can expand the bus to topologies with many initiators and targets, even though the communication over an AXI bus is limited to a single initiator and target.

Many of Xilinx’s partners have also adopted AMBA AXI4, AXI4-Lite, and AXI4-Stream as the primary communication bus in their devices.

There are 3 types of AXI4-Interfaces (AMBA 4.0):

• AXI4 (Full AXI4): For high-performance memory-mapped requirements.
• AXI4-Lite: For simple, low-throughput memory-mapped communication (for example, to and from control and status registers).
• AXI4-Stream: For high-speed streaming data.

How AXI became the most widespread AMBA interface

The protocol establishes the guidelines for how various chip modules might interact with one another; it necessitates a handshake-like process before any transmissions. Such a protocol connects and serves as an efficient means of data transfer between the chip’s existing components, enabling the establishment of a true “system” instead of a “collection” of modules.

AXI protocol Architecture 

The AXI protocol is a burst – based and defines 5 channels:

• 2 are used for reading transactions
  • read address
  • read data
• 3 are used for Write transactions
  • write address
  • write data
  • write response

The image below shows an AXI transaction consisting of multiple transfers

A transaction is an overall exchange of address and control information, data, and response over different channels in multiple bursts, each initiated by a handshake mechanism.

A transfer is a unit of data that is sent over a single channel. In the figure above, the read data is transferred in total 4 transfers.

 When the clock’s rising edge coincides with both the READY and VALID signals being high, a transfer takes place.

 For instance, the transfer is taking place on T3 in the picture below:

AXI Read Transactions

An AXI Read transaction requires multiple transfers on the 2 Read channels.

• First, the Address Read Channel is sent from the Master to the Slave to set the address and some control signals.
• Then the data for this address is transmitted from the Slave to the Master on the Read data channel.

Note that, as per the figure below, there can be multiple data transfers per address. This type of transaction is called a burst.

There is no separate channel for read response like write response channel. The slave signals read response for each transfer on the read data channel.  

AXI Write Transactions

An AXI Write transaction requires multiple transfers on the 3 Read channels.

• First, the Address Write Channel is sent Master to the Slave to set the address and some control signals.
• Then the data for this address is transmitted Master to the Slave on the Write data channel.
• Finally, the write response is sent from the Slave to the Master on the Write Response Channel to indicate if the transfer was successful.

The possible response values on the Write Response Channel are:

• OKAY (0b00): Normal access success. Indicates that normal access has been successful
• EXOKAY (0b01): Exclusive access okay.
• SLVERR (0b10): Slave error. The slave was reached successfully but the slave wishes to return an error condition to the originating master (for example, data read not valid).
• DECERR (0b11): Decode error. Generated, typically by an interconnect component, to indicate that there is no slave at the transaction address

Channel Handshake

A READY signal and a VALID signal are present on every AXI channel. These are employed to regulate and synchronize the transfer rate. It’s crucial to keep in mind that the source, or sender, indicates that data or control information is available by using the VALID signal. When the destination, or receiver, is truly able to use that data, it signals READY. 

The figure shown below the simple handshake mechanism, info is exchanged only when both the READY and VALID signals are asserted 

The AXI handshaking is seen in action in the figure below. Observe that regardless of which was claimed first, information transmission (shown by an arrow) only happens when both VALID and READY are high. Observe that AXI performs all transfers using the rising clock edge.

AXI handshake mechanism (adapted from AXI spec. v1.0)

According to the AXI specification, the READY signal of one component should never be dependent upon the VALID signal of another. READY is not required to wait for the VALID signal, but it can. 

By adhering to these guidelines, there is no possibility of a deadlock. Neither signal may be asserted if READY is dependent on VALID and VALID is dependent on READY as both signals depend on one another.

Full AXI4

While many of the optional signals in the entire AXI4 protocol are included, the timing diagram above just depicts the fundamental signals needed for a write transfer. The complete set of signals for the three AXI4 write channels is as follows:

Write Address Channel

• AWID – Write address ID. This signal is the identification tag for the write address group of signals.
• AWADDR – Write address. The write address gives the address of the first transfer in a write burst transaction.
• AWLEN – Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address. This changed between AXI3 and AXI4.
• AWSIZE – Burst size. This signal indicates the size of each transfer in the burst.
• AWBURST – Burst type. The burst type and the size information determine how the address for each transfer within the burst is calculated. The supported burst types are FIXED, INCR, and  WRAP.

In a fixed burst, the address is the same for every transfer in the burst.

In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer

A wrapping burst is similar to an incrementing burst, except that the address wraps around to a lower address if an upper address limit is reached.

• AWLOCK – Lock type. Provides additional information about the atomic characteristics of the transfer. Supported in AXI3 but in AXI4.
• AWCACHE – Memory type. This signal indicates how transactions are required to progress through a system.
• AWPROT – Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
• AWQOS – Quality of Service, QoS. The QoS identifier is sent for each write transaction. Implemented only in AXI4.
• AWREGION – Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces. Implemented only in AXI4.
• AWUSER – User signal. Optional User-defined signal in the write address channel. Supported only in AXI4.
• AWVALID – Write address valid. This signal indicates that the channel is signaling valid write address and control information.
• AWREADY – Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

Write Data Channel

• WID – Write ID tag. This signal is the ID tag of the write data transfer. Supported only in AXI3.
• WDATA – Write data.
• WSTRB – Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
• WLAST – Write last. This signal indicates the last transfer in a write burst.
• WUSER – User signal. Optional User-defined signal in the write data channel. Supported only in AXI4.
• WVALID – Write valid. This signal indicates that valid write data and strobes are available.
• WREADY – Write ready. This signal indicates that the slave can accept the written data.

Write Response Channel

• BID – Response ID tag. This signal is the ID tag of the written response.
• BRESP – Write a response. This signal indicates the status of the write transaction.
• BUSER – User signal. Optional User-defined signal in the write response channel. Supported only in AXI4.
• BVALID – Write response valid. This signal indicates that the channel is signaling a valid write response.
• BREADY – Response ready. This signal indicates that the master can accept a written response.

The complete set of signals for the two AXI4 read channels is as follows:

Read Address Channel

• ARID – Read address ID. This signal is the identification tag for the read address group of signals.
• ARADDR – Read address. The read address gives the address of the first transfer in a read burst transaction.
• ARLEN – Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address. This changed between AXI3 and AXI4.
• ARSIZE – Burst size. This signal indicates the size of each transfer in the burst.
• ARBURST – Burst type. The burst type and the size information determine how the address for each transfer within the burst is calculated. The supported burst types are FIXED, INCR and  WRAP.

In a fixed burst, the address is the same for every transfer in the burst.

In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer

A wrapping burst is similar to an incrementing burst, except that the address wraps around to a lower address if an upper address limit is reached.

• ARLOCK – Lock type. Provides additional information about the atomic characteristics of the transfer. Supported in AXI3 but not in AXI4.
• ARCACHE – Memory type. This signal indicates how transactions are required to progress through a system.
• ARPROT – Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
• ARQOS – Quality of Service, QoS. The QoS identifier is sent for each read transaction. Implemented only in AXI4.
• ARREGION – Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces. Implemented only in AXI4.
• ARUSER – User signal. Optional User-defined signal in the write address channel. Supported only in AXI4.
• ARVALID – Read address valid. This signal indicates that the channel is signaling valid read address and control information.
• ARREADY – Readaddress ready. This signal indicates that the slave is ready to accept an address and associated control signals.

Read Data Channel

• RID – Read ID tag. This signal is the identification tag for the read data group of signals generated by the slave.
• RDATA – Read data.
• RRESP – Read strobes. Read response. This signal indicates the status of the read transfer
• RLAST – Read last. This signal indicates the last transfer in a read burst.
• RUSER – User signal. Optional User-defined signal in the read data channel. Supported only in AXI4.
• RVALID – Write valid. This signal indicates that the channel is signaling the required read data
• RREADY – Read ready. This signal indicates that the master can accept the read data and response information.

The described AXI4 protocol is generic in that it supports a wide range of bus widths, doesn’t specify time, and offers a great deal of flexibility in terms of the transfers it can support. Xilinx provides data bus widths of 32 to 1024 in powers of two for full AXI4. Up to 256 burst lengths are supported. 

Many features many of which aren’t supported by the Xilinx IP aren’t of broad interest. Features like quality of service, low power interface, protection/cache bits, locked/exclusive access, etc. are examples of this type of feature. If bursting capabilities are required, these can be readily linked to static values to interface to the entire AXI4.

AXI-Lite Interface

The fourth iteration of the ARM Advanced Microcontroller Bus Architecture (AMBA) standard defines the Advanced eXtensible Interface 4 (AXI4) bus family. In 1996, AXI made its debut alongside the third iteration of AMBA, known as AXI3.

The AMBA specification defines 3 AXI4 protocols:

• AXI4: A high-performance memory-mapped data and address interface. Capable of Burst access to memory-mapped devices.
• AXI4-Lite: A subset of AXI, lacking burst access capability. Has a simpler interface than the full AXI4 interface.
• AXI4-Stream: A fast unidirectional protocol for transferring data from master to slave.

AXI4 Lite

Five channels make up the AXI4-Lite interface: Write Address, Write Data, Write Response, Write Address, and Write Address.

The key features of AXI4 lite are

• Each transaction burst length is 1.
•  data bus width is 32 bits or 64 bits and all transactions are the same width as the data bus. 
• All accesses are non – modifiable and non- bufferable hence AxCACHE is 0000.
• Exclusive accesses are not supported

The following table provides a detailed explanation of each signal on the AXI4-Lite Interface.

AXI4-Lite Read Transaction

Below, the sequence for an AXI4-Lite read is shown:

1. In addition to putting an address on the Read Address channel, the Master also asserts that the address is valid (ARVALID) and that it is prepared to accept data from the slave (READY).
2. To indicate that it is prepared to accept the address on the bus, the Slave claims ARREADY.
3. Since both ARVALID and ARREADY are asserted, the handshake takes place on the subsequent rising clock edge. Subsequently, the slave and master deassert ARREADY and ARVALID, respectively. (At this juncture, the desired address has reached the slave).
4. The required data is sent to the Read Data channel by the Slave, who then asserts RVALID to show that the data in the channel is legitimate. It is also possible for the slave to respond on RRESP, but this does not happen in this case.
5. The transaction is finished on the subsequent rising clock edge since both RREADY and RVALID are asserted. At this point, RREADY and RVALID can be released.

AXI4-Lite Read Transaction.

AXI4-Lite Write Transaction

Below, the sequence for an AXI4-Lite write is shown:

A description of the events in figure 4 follows:

1. The Write Address channel receives addresses from the Master, whereas the Write Data channel receives data. It also states that the address and data on the corresponding channels are legitimate by asserting AWVALID and WVALID. The Master also states that it is BREADY, meaning that it is prepared to hear back.
2. On the Write Address and Write Data channels, the Slave asserts AWREADY and WREADY, respectively.
3. The Write Address and Write Data channels both have Valid and Ready signals, thus when those signals are de-asserted, the handshakes on those channels take place. (The slave has the write address and data after both handshakes.)
4. A valid response is present on the Write response channel, as indicated by the Slave’s assertion of BVALID. (In this instance, the answer is 2’b00, which stands for “OKAY”).
5. When the subsequent rising clock edge occurs, the transaction is finished and the Ready and Valid signals are both high on the write response channel.

AXI4-Lite Write Transaction.

Comparison: AXI-Full vs AXI-Lite

Specifications

• AXI Infrastructure has AXI Full and AXI Lite protocols implemented in VHDL and fully compatible with AMBA Specifications.
• AXI Full and AXI Lite Interconnect are implemented in Shared access mode (Area Optimized).
• Configurable Multiple no of master devices and slave devices, depending on resources available on FPGA.
• AXI Full and AXI Lite interconnects also Support Read-only and Write-only Master devices and Slave devices resulting in reduced resource utilization.
• The code is written in generic VHDL so that it can be ported to a variety of FPGAs.
• Support for multiple clock domains.
• User logic can be connected to AXI Masters and AXI Slaves with a simple interface.
• Supports different interface data widths 8,16,32,64..512. And Address widths 8,16,32.

Design Considerations

Configuring the design for an AXI4- Lite Interface

The boundary of the Simulink design’s Cycle and Bit accurate FPGA sections is indicated by the Gateway In and Gateway Out blocks in the example_dds design. By “injecting” the right value onto the signals named phase_valid and phase_data that are connected to the output port of the Gateway In, the DDS Compiler frequency can be controlled. The phase_valid block’s Interface Options can be changed to do this, as demonstrated below.

Interface Options

The Interface is defined in Model Composer as a slave AXI4-Lite Interface, indicating that it would be converted to a top-level AXI4-Lite interface.

The following options are also of particular interest:

Auto-assign address offset

(Enable) This control indicates that automatic address offset assignment will occur in the design based on the number of distinct Gateway Ins mapped to the AXI4-Lite interface. Each Gateway is associated with a register within the AXI4-Lite Interface. By a 32-bit data width, addresses are byte-aligned. 

Address offset

(Disabled) Only when Auto-assign address offset is unchecked is this option enabled. The Address Offset can be manually overridden by the user.

Interface Name

Give this interface a special name. This name can be used in the design to distinguish between distinct AXI4-Lite interfaces.

Important: The Interface Name must be composed of alphanumeric characters (lowercase alphabetic) or an underscore (_) only, and must begin with a lowercase alphabetic character. ‘axi4_lite1‘ is acceptable, ‘1Axi4-Lite‘ is not.

Conclusion

In summary, The AXI interface family, primarily consisting of AXI-Full and AXI-Lite protocols, allows for a flexible on-chip communication framework; each of them is fine-tuned to meet certain needs. 

AXI-Full enables high-performance, burst-based transactions necessary in complex memory-mapped requirements, while AXI-Lite provides a lightweight, high-bandwidth approach for simple control/status operations. 

By mastering these interfaces, designers can optimize their FPGA designs for performance, efficiency, and scalability. Whether it involves complex systems or just simple control logic, the AXI protocols sit center stage in contemporary digital design and integration.

Frequently asked questions

Q: What is the difference between AXI lite and AXI full?

AXI4: A memory-mapped data and address interface with excellent performance. able to access memory-mapped devices in bursts. AXI4-Lite: A version of AXI without burst access. is more straightforward than the complete AXI4 interface.

Q: What is AXI’s full form?

A communication bus protocol for on-chip use, Advanced eXtensible Interface (AXI) is a component of the Advanced Microcontroller Bus Architecture specification (AMBA).

Q: What is the difference between AXI3 and AXI4-Lite?

Only burst lengths up to 16 beats are supported by AXI3. AXI4, however, allows for burst lengths of up to 256 beats. Write interleaving is supported by AXI3. There is no write interleaving support in AXI4.

Q: What is the data width of AXI Lite?

Interface data widths: AXI4: 32, 64, 128, 256, 512, or 1024 bits. AXI4-Lite: 32 bits.

Q: Is AXI a full duplex or half duplex?

A slave in AXI is allotted a minimum of 4 kb of address space, but a slave in AHB is assigned a minimum of 1 kb of address space. AHB does not offer a full-duplex manner of communication, whereas AXI does due to its several independent channels.