Multi DAC Synchronization in a JESD204B Environment
Synchronization is required in many systems like Multi-antenna communications systems, Phased array radars, Magnetic resonance imaging etc. Most systems that require multiple synchronized signal chains also require synchronization of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
If the Latency between the JESD204B interface in the FPGA and DAC Output is always fixed and constant, then we say that the DAC output is synchronized. Latency from the frame-based data input at the TX to the frame-based data output at the RX. Latency should be programmable and repeatable over power cycles and re-sync events.
What will you learn from this whitepaper :
- Basic concept of synchronization.
- Requirements for a JESD204B System synchronization.
- Methods to achieve Multi Clock Synchronization.
- Challenges faced in achieving Multi Clock Synchronization.
- Synchronization of digital blocks such as NCO in different DAC devices.
- Concept of Deterministic latency in JESD204B.
- Challenges faced in achieving the Multi DAC Synchronization.
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